1989 · 10 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware-software Co-designSystem-on-chip DesignCache CoherenceCachingInstruction Set ArchitectureMemory Hierarchy DesignMemory Subsystem DesignMultiprocessor SystemsCache ArchitectureCache DesignCache HierarchiesCache Hierarchy DesignCache Memory DesignProcessor ArchitectureProcessor SystemsRisc Architectures
By designing a system specifically targeted to support a high-performance RISC processor it is possible to achieve total system performance in balance with processor performance. However, to achieve this goal careful attention must be paid to the interactions between processor, memory, and I/O. In particular, the memory system must be designed to handle the voracious appetite of the RISC processor without starving I/O. The authors describe a third-generation RISC processor with advanced attributes resulting in a cycles per instruction average of 1.25 and the memory and I/O system which support it. Additionally, they describe attributes that allow the implementation of multiple-processor systems with cache coherency.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>