Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

Abstract

This paper explores the area-throughput trade-off for an ASIC implementation of the advanced encryption standard (AES) algorithm in a 0.18 /spl mu/m CMOS technology. Three different pipelined implementations of the AES algorithm are presented which provide a throughput range between 15.7 to 77.6 Gbits/s with an area cost of 116 to 473 Kgates. Therefore, the AES algorithm in the counter mode of operation can be used to generate cryptographically secure pseudorandom numbers at a throughput rate of multiten Gbits/s. Thus it becomes available for encryption on an optical link.

References

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	Year	Citations
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists A.J. Elbirt, Wai-Yeung Yip, B. Chetwynd, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringInformation SecurityHardware AlgorithmComputer ArchitectureBlock Cipher	2001	275
Design and performance testing of a 2.29-GB/s rijndael processor Ingrid Verbauwhede, Patrick Schaumont, Henry Kuo IEEE Journal of Solid-State Circuits Hardware SecuritySystem On ChipElectrical EngineeringLow-power ElectronicsPerformance Testing	2003	224
Hardware Evaluation of the AES Finalists. Tetsuya Ichikawa, Tomomi Kasuya, Mitsuru Matsui EngineeringHardware AlgorithmComputer ArchitectureSystem-level DesignBlock Cipher	2000	96
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technology Henry Kuo, Ingrid Verbauwhede, Patrick Schaumont EngineeringVlsi DesignComputer ArchitectureμM Cmos TechnologyBlock Cipher	2003	19

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