2004 · 38 citations · 4 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureCryptographySystem-on-chip DesignCmos Circuit DesignCryptographic AlgorithmsCryptographic ArchitectureCryptographic ImplementationData EncryptionLow-power Digital Circuit DesignAdvanced Encryption StandardAsic ImplementationEncryptionHigh-speed Cmos DesignPseudorandom GeneratorsSpeed Trade-offThroughputThroughput Trade-offs
This paper explores the area-throughput trade-off for an ASIC implementation of the advanced encryption standard (AES) algorithm in a 0.18 /spl mu/m CMOS technology. Three different pipelined implementations of the AES algorithm are presented which provide a throughput range between 15.7 to 77.6 Gbits/s with an area cost of 116 to 473 Kgates. Therefore, the AES algorithm in the counter mode of operation can be used to generate cryptographically secure pseudorandom numbers at a throughput rate of multiten Gbits/s. Thus it becomes available for encryption on an optical link.
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Hardware Evaluation of the AES Finalists.
Tetsuya Ichikawa, Tomomi Kasuya, Mitsuru Matsui · 2000 · 96 citations