An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists

TLDR

Technical analysis for selecting AES candidates includes efficiency testing of hardware and software implementations, and FPGAs are attractive for hardware due to agility, security, and higher performance. The study investigates FPGA implementations of AES candidate algorithms and compares them to identify the most suitable candidate for commercial FPGA deployment. The authors explored multiple architectural options for each algorithm, emphasizing high‑throughput designs to meet security needs of high‑bandwidth applications. The comparative analysis of implementations will determine the most suitable AES candidate for hardware implementation on commercially available FPGAs.

Abstract

The technical analysis used in determining which of the potential Advanced Encryption Standard candidates was selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as field-programmable gate arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms, as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high-throughput implementations, which are required to support security for current and future high bandwidth applications. Finally, the implementations of each algorithm will be compared in an effort to determine the most suitable candidate for hardware implementation within commercially available FPGAs.