A 4.3GB/s mobile memory interface with power-efficient bandwidth scaling

Abstract

A 4.3GB/s mobile memory interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.