2009 · 20 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignDevice ScalingEnergy-efficient Mobile ComputingMemory DevicesMemory Subsystem DesignPower ManagementBandwidthBandwidth ScalingClocking ArchitectureCmos ScalingMemory Interface ArchitectureMemory Interface DesignPower EfficiencyPower-efficient Architecture
A 4.3GB/s mobile memory interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A pausable clocking architecture enables fast power state transitions. The controller interface achieves 3.3mW/Gb/s power efficiency at 4.3GB/s data bandwidth, and supports better than 5mW/Gb/s operation over a range from 0.03 to 4.3GB/s.
13
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
John W. Poulton, R. Palmer, Andrew M. Fuller et al. · IEEE Journal of Solid-State Circuits · 2007 · 240 citations
Engineering, Computer Engineering, Electrical Engineering +17