A 22GS/s 6b DAC with integrated digital ramp generator

Peter Schvan, D. Pollex, T. Bellingrath

2005 · 51 citations · 6 references

Concepts

Abstract

A 22GS/s 6b DAC is presented that includes a digital ramp pattern generator. The DAC core and ramp generator consume 2W and 1.2W respectively operating from 3.3V. The DAC produces a differential signal up to 1.3V/sub pp/ DNL<0.5LSB and INL<0.9LSB are measured. The highest glitch energy is 0.5pVs. Settling times are 70 and 40ps for full- and half-scale transitions, respectively.

References

6