ESD protection of double-diffusion devices in submicron CMOS processes

Abstract

The device level strategy for ESD protection of "free" double diffusion 12 V and 20 V LDMOS devices, realized in a 3.3 V CMOS process, is presented. The self-protection capabilities and limitations of LDMOS devices have been analyzed, along with complementary snapback TFO and SCR devices, under ESD stress conditions. Optimal device type and parameters have been determined.