Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking

Abstract

Network-on-chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on today's high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A method is presented to determine the clock rate distribution among cores. Experimental results for the ITC '02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.