Power-aware noc reuse on the testing of core-based systems

Abstract

This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider power consumption during test, while minimizing the system testing time. Experimen- tal results with the ITC'02 SoC benchmarks show that al- though power constraints can preclude the full exploration of the network parallelism, this platform is still a powerful mechanism for the system test time reduction at a very low cost.