2002 · 20 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingConfigurable Logic BlocksDigital Logic DesignDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureLookup TablesDigital FilteringFilter ArchitectureFilter CircuitsFiltersHardware-based FilteringReal-time ProcessingThroughputThroughput Improvement
A set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. The main results show that the canonical form presents less occupation and higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7 MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.
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