High performance tantalum carbide metal gate stacks for nMOSFET application

Abstract

A systematic study is performed on tantalum carbide (TaC) metal electrode on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and HfSiON dielectrics using conventional CMOS process. TaC's effective work function (EWF) is estimated to be 4.28 eV on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> using Vfb~EOT methodology, where both interfacial oxide and high-K film thickness are varied and thus charge effect is corrected successfully. Investigation of the EWF dependence on underlying dielectrics reveals that TaC EWF on HfSiON is about 0.17eV higher than that on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . This phenomenon cannot be explained by the usual metal induced gap states (MIGS) theory. In addition, mobility higher than 90% of poly/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> reference and EOT scaling down to 12.5A has been achieved. Reduction of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness is identified as an effective approach to suppress charge trapping in the gate stack. With reduced thickness, threshold voltage stability and electron mobility are significantly improved. All these results prove that TaC/high-K stack is a promising candidate in nMOSFET application