Publication | Closed Access
Multi-chip packaging technology for VLSI-based systems
39
Citations
1
References
1987
Year
Unknown Venue
Electrical EngineeringConventional PackagingEngineeringChip-scale PackageAdvanced Packaging (Semiconductors)MicrofabricationChip On BoardMulti-chip Packaging TechnologyComputer EngineeringComputer ArchitectureChip AttachmentSolder Bump BondingVlsiMultichip Packaging TechnologyElectronic PackagingMicroelectronicsPackage IntegrationInterconnect (Integrated Circuits)
A multichip packaging technology using silicon substrate and solder bump bonding will be presented. Compared to conventional packaging it affords three times the operating frequency. Additionally, packaged size and power dissipation are reduced by a factor of 7 and 30%, respectively.
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