Publication | Closed Access
A high bandwidth superscalar microprocessor for multimedia applications
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2003
Year
Unknown Venue
Hardware SecuritySystem On ChipMemory ArchitectureEngineeringScratchpad RamHigh-performance ArchitectureMultimedia ProcessorComputer EngineeringComputer ArchitectureSystems EngineeringComputer ScienceEmbedded SystemsParallel ComputingPerformance Counting FacilitiesProcessor ArchitectureB External BusMulti-channel Memory ArchitectureMultimedia Applications
This 250 MHz 2-way superscalar MIPS-compatible embedded microprocessor is targeted for use in high-end consumer electronics, game, and network markets. The microprocessor features a high-bandwidth (2.0 GB/s peak) 128 b external bus. Internal datapaths and load/store paths to and from the caches are also 128 b wide. Numerous functional enhancements are incorporated, including a 128 b SIMD instruction set for multimedia support, an integrated scratchpad RAM (SPRAM), and a comprehensive set of debug and performance counting facilities.