2003 · 22 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSystem-on-chip DesignInstruction Set ArchitectureMemory Hierarchy DesignMemory Subsystem DesignMicroarchitecture DesignProcessor Core DesignProcessor MicroarchitectureCache Memory DesignInstruction Set DesignInstruction Set MicroarchitectureLoad PathsMemory Interface DesignMemory Interface IntegrationScratchpad MemorySuperscalar Microarchitecture
This 250 MHz 2-way superscalar MIPS-compatible embedded microprocessor is targeted for use in high-end consumer electronics, game, and network markets. The microprocessor features a high-bandwidth (2.0 GB/s peak) 128 b external bus. Internal datapaths and load/store paths to and from the caches are also 128 b wide. Numerous functional enhancements are incorporated, including a 128 b SIMD instruction set for multimedia support, an integrated scratchpad RAM (SPRAM), and a comprehensive set of debug and performance counting facilities.