A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications

Abstract

3D sub-system integration of logic and DRAM with TSV is desirable for wide memory bandwidth and reduced power for mobile applications. However, its manufacturing cost, along with testing and heat dissipation, remains to be outstanding issues. A new integration technology platform, InFO, is proposed to address it. In this paper, we compare three main 3D integration architectures: InFO_PoP, FC_PoP and 3DIC with TSV based on mobile product requirements, including system power- performance-profile (form factor), heat dissipation, memory bandwidth and production cycle-time along with cost. InFO not only best optimizes and achieves the requirements, but also more readily integrates partitioned-chips, which further impacts on the manufacturing of the logic/DRAM sub-system.