A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation

F. Hayashi, H. Ohkubo, Tomoko Takahashi, S. Horiba, K. Noda, T. Uchida, T. Shimizu, N. Sugawara, S. Kumashiro

2002 · 21 citations · 0 references

Concepts

Abstract

A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current drivability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 /spl mu/m design rule 64 kbit SRAMs without a boosted word-line scheme.