Performance and Reliability of 2-Transistor FN/FN Flash Arrays with Hafnium Based High-K Inter-Poly Dielectrics for Embedded NVM

Abstract

Flash memories are difficult to embed in advanced CMOS generations, which is largely due to the nonscaling high program and erase (P/E) voltages; typically V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PE</sub> ap15V for cells operated by Fowler-Nordheim (FN) tunneling. Besides, for memories of only a few Mbytes, the need for these high voltages leads to a bad array-to-periphery area efficiency, resulting in a relatively large module size. Therefore, VPE reduction is an important driver for embedded flash scaling. Several flash-like technologies with lower P/E voltages have been explored over the past few years, e.g., nanocrystal and nitride memories. However, reliability, especially at high temperatures, is still an issue for these concepts. Therefore, in this work, we use the proven floating gate (FG) concept, but with the innovative approach of applying high-K materials in the inter-poly dielectric (IPD) between control gate (CG) and FG in order to increase the coupling ratio alphaCG, thus reducing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PE</sub> . The high-K IPD enables reduction of the equivalent oxide thickness (EOT) without compromising the data retention by leakage currents. To increase the (statistical) relevance of this work beyond that of single cell studies, we used full flash arrays