The Air Spacer Technology for Improving the Cell Distribution in 1 Giga Bit NAND Flash Memory

Abstract

Recently the cell integration density of NAND flash memory increases rapidly due to its simple structure suitable for high resolution lithography. However as the cell integration density increases, NAND flash memory cell shows the problem of increased parasitic capacitance between the cells. The problems are generated by the floating-gate interference during cell operation. In order to reduce the floating gate interference, it is necessary to adopt low-k dielectric material. In this work, we would like to propose the air spacer which has the lowest dielectric constant. We applied the air spacer technology on poly-Si/W six stack gate of 90 nm design-rule NAND flash device for the first time, which improved the cell operation characteristics