A quad-band low power single chip direct conversion CMOS transceiver with ΣΔ-modulation loop for GSM

Abstract

This paper presents a fully integrated quad band GSM transceiver with a new sigma-delta modulator architecture designed in a standard 120 nm CMOS technology. The fully integrated VCO operates at 4 GHz with a frequency range that can be programmed by 10 bit. The output power of the transmitter is 8 dBm and no TX SAW filter is needed due to the low phase noise of -162 dBc/Hz at 20 MHz offset frequency. The inband phase noise of the synthesizer is only -100 dBc/Hz and an overall phase noise error of 1.6/spl deg/ rms has been measured. The receiver has constant gain of 57 dB and fits to a baseband processor providing a 14 bit ADC. The noise figure in all bands is below 3 dB typically. The chip is housed in a 48 pin VQFN package.