Characterization and modeling of clock skew with process variations

Abstract

A new compact model for on-chip clock skew as a function of device, interconnect, and system parameter variations is derived. Unlike previous models that describe qualitative behavior of clock skew components, the new model provides a closed form expression for each clock skew component. An example of clock skew components for a typical design using 0.18 /spl mu/m CMOS technology is investigated.