2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture

With multi-phase clocking, it is possible to attain a higher operating speed than the internal clock frequency determined by the device performance limitation. When multi-phase clocking is to be applied to larger die sizes or to multi-channel communications, however, it is extremely difficult to distribute the multi phase clock signals to distant local areas without generating inter-phase skew. To achieve a small area for clock distribution, the multi-phase clock generator reported here uses the delay compensation technique. Because this generator does not require a feedback loop, it is compact, adding only a small amount to chip area. Further, it produces accurate phase differences between multi-phase clock signals. Multi-clock generators of this type are applied to 2.5 GHz 4-phase clock distribution of an 8-channel receiver, fabricated with 0.13 /spl mu/m CMOS technology, and operating at 5 Gb/s.