VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)

Balsha R. Stanisic, Mark Brown

2003 · 13 citations · 3 references

Concepts

Abstract

A description is given of techniques for simulation modeling and of a physical design verification methodology for assuring simulation and interconnection correspondence. Following the introductory material, details of the simulation model are presented. Then a description of a physical design verification methodology is given, followed by results from current designs, and key points are summarized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

References

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