A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

Abstract

Describes a 256-word /spl times/ 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-V/sub t/ usage, and 50% keeper downsizing. Gate-source underdrive of -V/sub cc/ on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-V/sub t/ bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703/spl times/ bitline active leakage reduction, enabling continued V/sub t/ scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented.