Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems

Abstract

A new circuit configuration, the differential cascode voltage switch with the pass-gate logic tree (DCVSPG), is presented. In this circuit family, the authors use the pass-gate logic tree to replace the nMOS logic tree in the conventional DCVS circuit in order to eliminate the floating-node problem. By eliminating the floating-node, the DCVSPG shows superior performance, silicon area and power consumption. Moreover, the dynamic DCVSPG also provides the leverage of relieving the charge redistribution concern and reinforces the signal integrity in the typical pre-charge dynamic circuits. The principle of operation of the DCVSPG is explained. A simple synthesis technique of the pass-gate logic tree is discussed. Finally, a 64-bit carry look-ahead adder is designed by using the static DCVSPG circuit. A nominal cycle time (T/sub a/=22 degrees C and power supply of 2.5 V) of 2.0 ns is obtained by using a 0.5 mu m CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>