CMOS implementation of a 32 b computer

Abstract

A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described. It operates at a cycle time of 28 ns and is compatible with an existing computer architecture. The chip set is fabricated in a 1.5- mu m n-well, double-layer-metal CMOS process and includes over 650000 transistors. The CPU is a six-level pipeline engine built around three semiautonomous pipes. These provide simultaneous instruction prefetch and decode, specifier decode and execution, memory management, and I/O access. The CPU averages nine cycles/instruction on typical benchmarks. Chip functionality is verified through test vectors at the pins, with stuck-at fault coverage greater than 95%, and complete control store and cache tests. Summaries of process characteristics and physical specifications are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>