Determination of the line edge roughness specification for 34 nm devices

Abstract

The impact of gate line edge roughness (LER) on 70 nm MOS devices was measured experimentally and used to validate an enhanced statistical technique for evaluating LER effects on devices. The technique was used to determine that LER in 34 nm devices will need to be limited to 3 nm. Effect of LER spectrum on wide and narrow devices is discussed, as well as an approach for correcting experimental current measurements for LER.