1985 · 13 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignConfigurable Logic BlocksDelay ModelingTiming AnalysisHigh-speed Circuit DesignHigh-speed Cmos DesignHigh-speed Logic DesignSignal Propagation Delay
This paper will report on a 9K ECL array with a 99.6ps propagation delay. The chip is ECL 10K or 100K compatible, consumes 20W typical and has 256 logic pins plus 64 supply pins.
1
A masterslice LSI for subnanosecond random logic
W. Braeckelmann, H. Fritzsche, F. Kroos et al. · 1977 · 18 citations
Engineering, Computer Engineering, Electrical Engineering +10