2002 · 13 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignCmos Circuit DesignDigital Signal ProcessingPulse Processing ElectronicsRadar Signal ProcessingRadar SystemsCell Library DesignDigital BeamformingEqualizationHigh-speed Cmos DesignPulse CompressionRadar Hardware ArchitectureSystolic Array DesignSystolic Arrays
A very-high-speed radar front-end signal processing CMOS VLSI chip-set using a fully efficient bit-level systolic array architecture has been developed by MIT Lincoln Laboratory. The chip-set performs baseband quadrature sampling, channel equalization, pulse compression, and digital beamforming. The highly pipelined fully efficient bit-level systolic architecture and the highly optimized scalable CMOS VLSI cell library design give the chip-set extremely high performance. The chip-set uses an efficient 4:1 down-sampling baseband quadrature sampling architecture with reduced computational requirement. The chip-set and the cell library have potential in a variety of applications such as communications and medical imaging.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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P.-E. Danielsson · IEEE Transactions on Computers · 1984 · 58 citations
Multibit convolution using a bit level systolic array
J.G. McWhirter, D. Wood, K. Wood et al. · IEEE Transactions on Circuits and Systems · 1985 · 17 citations