Simulating the future kilo-x86-64 core processors and their infrastructure

Abstract

The continuous improvements offered by the silicon technology enables the integration of always increasing number of cores on a single chip. Following this trend, it is expected to approach microprocessor architectures composed of thousands of cores (i.e., kilo-core architectures) in the next future. To cope with the increasing demand for high performance systems, many-core designs rely on integrated network-on-chips to deliver the correct bandwidth and latency for the inter-core communications. In this context, simulation tools represent a crucial factor for designing architectures at such scale of integration. The efficient simulation of the interconnection network along with the overall architecture (i.e., cores, cache memories, accelerators, etc.) still represents a complete open issue. This paper proposes a framework based on the COTSon simulator, able of scaling towards heterogeneous kilo-core architectures. Compared with current state-of-the-art architectural simulators, our framework provides not only a full-system architectural simulator, but a full-integrated accurate network-on-chip simulator. The framework shows a well balanced trade-off between simulation speed and accuracy, supporting the power consumption estimation. Experimental results demonstrate the ability of our framework to correctly simulate a large many-core machine and its interconnection network, considering different traffic patterns.