Procedia Computer Science · 2015 · 10 citations · 14 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingVlsi DesignFault Tolerance DesignHardware Fault ToleranceInterconnect DesignNetwork-on-chip DesignRoutingRouting ArchitectureDeflection RoutingFault Tolerant ArchitecturesFault-tolerant ArchitectureFault-tolerant Network DesignFault-tolerant NetworksFault-tolerant RoutingNetwork-on-chip ArchitecturesPermutation Routing
Deflection routing is a promising approach for energy and hardware efficient NoCs. Future VLSI designs will have an increasing susceptibility to failures and breakdowns. The inherent redundancy of NoCs can be used to tolerate such failures. We extended the non-fault-tolerant CHIPPER router architecture to enable fault-tolerance. This architecture is based on deflection routing and utilizes a permutation network instead of a crossbar. Compared to a crossbar based design, a permutation network allows a faster and smaller router design. Simulations of a 8 × 8 network and more than 30.000 flit injections show, that our router architecture is competitive with existing crossbar based fault-tolerant router architectures.
14
Shekhar Borkar · Proceedings - ACM IEEE Design Automation Conference · 2007 · 955 citations
On-Chip Interconnection Architecture of the Tile Processor
David Wentzlaff, Patrick Griffin, Henry Hoffmann et al. · IEEE Micro · 2007 · 682 citations
On-Chip Interconnection Architecture of the Tile Processor
David Wentzlaff, Patrick Griffin, Henry Hoffmann et al. · IEEE Micro · 2007 · 574 citations
A 5-GHz Mesh Interconnect for a Teraflops Processor
Yatin Hoskote, Sriram Vangal, A. Singh et al. · IEEE Micro · 2007 · 518 citations