Voting Gate

A Voting Gate is a logical gate in fault tree analysis that belongs to the class of logic gates used to model system reliability, distinguished by its requirement that a specified minimum number of input events (out of a total) must occur for the output event to be triggered.

7

Publications

350

Citations

19

Authors

7

Institutions

Publications per year

2017–2026

1

Variants

K-out-of-n Gate

Authors

19

  1. MM
    Massimo Macucci

    University of Pisa, Italy

    2 publications · 51 citations

    2

    h-index

  2. GI
    Giuseppe Iannaccone

    University of Pisa, Italy

    2 publications · 51 citations

    2

    h-index

  3. BP
    B. Pellegrini

    University of Pisa, Italy

    1 publications · 30 citations

    1

    h-index

  4. JN
    Jitendra Nath Roy

    National Institute of Technology Agartala, India

    1 publications · 14 citations

    1

    h-index

  5. MG
    M. Gattobigio

    Istituto Nazionale di Fisica Nucleare, Italy

    1 publications · 21 citations

    1

    h-index

1–5 of 19

Venues

  1. Journal of Optical Communications

    1 publications · 14 citations

    1

    h-index

  2. 1

    h-index

  3. Public Administration Review

    PAR · 1 publications · 71 citations

    1

    h-index

  4. Journal of Computer and System Sciences

    1 publications · 27 citations

    1

    h-index

  5. Microelectronics Reliability

    1 publications · 72 citations

    1

    h-index

1–5