Timing-overhead Tradeoffs
Timing-Overhead Tradeoffs is a performance metric in logic locking that quantifies the balance between circuit delay introduced by obfuscation techniques and the resulting security overhead, distinguishing it from functional or area-based evaluation criteria by focusing specifically on temporal efficiency and protection cost.
13
Publications
311
Citations
41
Authors
21
Institutions
Publications per year
2017–2026
4
Parents
13
Faster and Timing-Attack Resistant AES-GCM
Emilia Käsper, Peter Schwabe · Lirias (KU Leuven) · 2009 · 71 citations · Full text
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
Wan‐Ping Lee, Hung‐Yi Liu, Yao‐Wen Chang · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2007 · 24 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 13
41
2
h-index
2
h-index
2
h-index
1
h-index
1
h-index
1–5 of 41
21

National Taiwan University
Taipei, Taiwan
2 h-index
6 publications
243 citations
University of California System
Oakland, United States
1 h-index
2 publications
26 citations
MediaTek (Taiwan)
Hsinchu, Taiwan
1 h-index
1 publications
35 citations
Eindhoven University of Technology
Eindhoven, The Netherlands
1 h-index
1 publications
71 citations

University of Central Florida
Orlando, United States
1 h-index
3 publications
66 citations
California Southern University
Chandler, United States
1 h-index
8 publications
88 citations
North Carolina State University
Raleigh, United States
1 h-index
2 publications
22 citations
University of Florida
Gainesville, United States
1 h-index
1 publications
11 citations
1–8 of 21
ICCAD · 1 publications · 24 citations
1
h-index
1 publications · 35 citations
1
h-index
1 publications · 10 citations
1
h-index
Conference · 1 publications · 11 citations
1
h-index
Conference · 1 publications · 57 citations
1
h-index
1–5