Yu-Shih Su

Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs

Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang et al. · 2009 · 35 citations

Engineering, Vlsi Design, Computer Architecture +18

Performance Optimization Using Variable-Latency Design Style

Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010 · 35 citations

Logic Synthesis, Engineering, Vlsi Design +14

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2010 · 32 citations

Engineering, Vlsi Design, Computer Architecture +20

An efficient mechanism for performance optimization of variable-latency designs

Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang et al. · Proceedings - ACM IEEE Design Automation Conference · 2007 · 26 citations

Logic Synthesis, Engineering, Circuit Design +14

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs

Chiao-Ling Lung, Yu-Shih Su, Hsih-Hsiu Huang et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2013 · 20 citations

Hardware Security, 3D Ic Architecture, Electrical Engineering +14