Timing Signoff

Timing Signoff is a formal verification milestone in digital circuit design that represents the final assessment of timing constraints to ensure that a chip meets its performance specifications under all operating conditions.

19

Publications

439

Citations

38

Authors

14

Institutions

Publications per year

2017–2026

2

Authors

38

  1. AB
    Andrew B. Kahng

    University of California San Diego, United States

    9 publications · 212 citations

    9

    h-index

  2. WJ
    Wei-Ting Jonas Chan

    University of California San Diego, United States

    4 publications · 70 citations

    4

    h-index

  3. AS
    Ashok S. Vydyanathan

    Myongji University, South Korea

    3 publications · 63 citations

    3

    h-index

  4. LG
    Luís Guerra e Silva

    Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento, Portugal

    3 publications · 42 citations

    3

    h-index

  5. SH
    Seung-Soo Han

    Myongji University, South Korea

    3 publications · 63 citations

    3

    h-index

1–5 of 38

Venues

  1. 2

    h-index

  2. 1

    h-index

  3. 1

    h-index

  4. 1

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  5. Design, Automation, and Test in Europe

    Conference · 1 publications · 14 citations

    1

    h-index

1–5