Timing Signoff
Timing Signoff is a formal verification milestone in digital circuit design that represents the final assessment of timing constraints to ensure that a chip meets its performance specifications under all operating conditions.
19
Publications
439
Citations
38
Authors
14
Institutions
Publications per year
2017–2026
2
Parents
19
Machine-learning-based dynamic IR drop prediction for ECO
Yen-Chun Fang, Heng-Yi Lin, Min-Yan Su et al. · 2018 · 65 citations
Andrew B. Kahng · 2015 · 48 citations
1–5 of 19
38
9
h-index
4
h-index
3
h-index
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento, Portugal
3 publications · 42 citations
3
h-index
3
h-index
1–5 of 38
14
University of California San Diego
San Diego, United States
10 h-index
32 publications
671 citations
Myongji University
Seoul, South Korea
3 h-index
3 publications
63 citations
Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento
Lisbon, Portugal
3 h-index
5 publications
74 citations
University of Illinois Urbana-Champaign
Urbana, United States
2 h-index
5 publications
88 citations
Synopsys (United States)
Mountain View, United States
2 h-index
4 publications
91 citations
Cadence Design Systems (United States)
San Jose, United States
2 h-index
4 publications
60 citations
IBM (United States)
Armonk, United States
1 h-index
2 publications
20 citations

Illinois Institute of Technology
Chicago, United States
1 h-index
1 publications
10 citations
1–8 of 14
Conference · 2 publications · 38 citations
2
h-index
1 publications · 11 citations
1
h-index
Conference · 1 publications · 10 citations
1
h-index
1 publications · 14 citations
1
h-index
Conference · 1 publications · 14 citations
1
h-index
1–5