Technology Mapping For Power

Technology Mapping for Power is a systematic methodology within electronic design automation that transforms a logical circuit representation into a physically implementable netlist optimized for minimal power consumption while adhering to technological constraints and performance requirements.

21

Publications

799

Citations

39

Authors

18

Institutions

Publications per year

2017–2026

0

Authors

39

  1. JC
    Jason Cong

    University of California, Los Angeles, United States

    3 publications · 199 citations

    3

    h-index

  2. SK
    Srinivas Katkoori

    University of South Florida, United States

    3 publications · 86 citations

    3

    h-index

  3. DC
    Deming Chen

    University of Illinois Urbana-Champaign, United States

    3 publications · 199 citations

    3

    h-index

  4. WM
    Wai-Kei Mak

    National Tsing Hua University, Taiwan

    3 publications · 86 citations

    3

    h-index

  5. LH
    Lei He

    University of California, Los Angeles, United States

    2 publications · 73 citations

    2

    h-index

1–5 of 39

Venues

  1. Journal of Low Power Electronics

    1 publications · 21 citations

    1

    h-index

  2. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 1 publications · 38 citations

    1

    h-index

  3. cIRcle (University of British Columbia)

    Repository · 1 publications · 22 citations

    1

    h-index

  4. 1

    h-index

  5. 1

    h-index

1–5