Technology Mapping For Power
Technology Mapping for Power is a systematic methodology within electronic design automation that transforms a logical circuit representation into a physically implementable netlist optimized for minimal power consumption while adhering to technological constraints and performance requirements.
21
Publications
799
Citations
39
Authors
18
Institutions
Publications per year
2017–2026
0
Parents
21
Technology Mapping for Low Power
1993 · 137 citations
Engineering, Computer Engineering, Electrical Engineering +13
Technology mapping for lower power
Vivek Tiwari, Pranav Ashar, Sharad Malik · 1993 · 122 citations · Full text
Management, Technology Management, Digital Transformation +5
Low-power technology mapping for FPGA architectures with dual supply voltages
Deming Chen, Jason Cong, Fei Li et al. · 2004 · 55 citations
1–5 of 21
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18
University of Illinois Urbana-Champaign
Urbana, United States
3 h-index
5 publications
194 citations
National Tsing Hua University
Hsinchu, Taiwan
3 h-index
4 publications
95 citations
University of California, Los Angeles
Los Angeles, United States
3 h-index
7 publications
382 citations
University of South Florida
Tampa, United States
3 h-index
8 publications
220 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
1 h-index
2 publications
44 citations
National Chung Cheng University
Minxiong, Taiwan
1 h-index
3 publications
36 citations
Software and Engineering Associates (United States)
Carson City, United States
1 h-index
1 publications
126 citations
The University of Texas at Austin
Austin, United States
1 h-index
2 publications
26 citations
1–8 of 18
1 publications · 21 citations
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TODAES · 1 publications · 38 citations
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Repository · 1 publications · 22 citations
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1 publications · 126 citations
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1 publications · 18 citations
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1–5