Concepedia

Store Buffering

Store Buffering is a memory consistency mechanism within the memory hierarchy that temporarily holds pending store operations in a processor-specific buffer to decouple instruction execution from memory system timing, thereby enabling speculative and out-of-order execution while maintaining architectural consistency.

22

Publications

1.2K

Citations

65

Authors

27

Institutions

Publications per year

2017–2026

2

Parents

Publications

22

Computing Architectural Vulnerability Factors for Address-Based Structures

Arijit Biswas, Paul Racunas, Razvan Cheveresan et al. · ACM SIGARCH Computer Architecture News · 2005 · 184 citations

, , +15

Computing Architectural Vulnerability Factors for Address-Based Structures

A. Biswas, Paul Racunas, Razvan Cheveresan et al. · 2005 · 155 citations

, , +15

Mechanisms for store-wait-free multiprocessors

Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi et al. · 2007 · 142 citations · Full text

, , +17

Sentinel scheduling for VLIW and superscalar processors

Scott Mahlke, William Y. Chen, Wen‐mei Hwu et al. · 1992 · 120 citations · Full text

, , +15

Dynamic partial order reduction for relaxed memory models

Naling Zhang, Markus Kusano, Chao Wang · 2015 · 89 citations

, , +17

1–5 of 22

Authors

65

  1. JD
    Joseph Devietti

    University of Washington, United States

    3 publications · 126 citations

    3

    h-index

  2. MK
    Markus Kusano

    Virginia Tech, United States

    2 publications · 99 citations

    2

    h-index

  3. PI
    Pablo Ibáñez

    Universidad de Zaragoza, Spain

    2 publications · 47 citations

    2

    h-index

  4. AR
    Alberto Ros

    Universidad de Murcia, Spain

    2 publications · 26 citations

    2

    h-index

  5. LC
    Luís Ceze

    University of Washington, United States

    2 publications · 111 citations

    2

    h-index

1–5 of 65

Institutions

27

  1. University of Toronto

    Toronto, Canada

    3 h-index

    3 publications

    165 citations

  2. Carnegie Mellon University

    Pittsburgh, United States

    3 h-index

    8 publications

    608 citations

  3. Virginia Tech

    Blacksburg, United States

    3 h-index

    8 publications

    409 citations

  4. Universidad de Murcia

    Murcia, Spain

    2 h-index

    2 publications

    26 citations

  5. University of Washington

    Seattle, United States

    2 h-index

    10 publications

    555 citations

  6. Intel (United States)

    Santa Clara, United States

    2 h-index

    7 publications

    839 citations

  7. Universitat Politècnica de Catalunya

    Barcelona, Spain

    2 h-index

    2 publications

    47 citations

  8. Princeton University

    Princeton, United States

    2 h-index

    2 publications

    339 citations

1–8 of 27

Venues

  1. ACM SIGARCH Computer Architecture News

    3 publications · 221 citations

    3

    h-index

  2. ACM SIGPLAN Notices

    2 publications · 36 citations

    2

    h-index

  3. arXiv (Cornell University)

    Repository · 1 publications · 39 citations

    1

    h-index

  4. Psychological Review

    1 publications · 11 citations

    1

    h-index

  5. Quarterly Journal of Experimental Psychology

    QJEP · 1 publications · 15 citations

    1

    h-index

1–5