Paul Racunas - Concepedia

Author

Paul Racunas

Intel (United States)

Also Known As

P. Racunas, Paul Racunas, Racunas, Paul

Publications

705

Citations

H-Index

Concepts

All Affiliations

Intel (United States)Nvidia (United States)University of Michigan Princeton University

About

Paul Racunas is an author at Intel (United States) specializing in computer architecture, computer science, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	685
2	Computer Engineering	9	9	685
3	Computer Science	9	9	685
4	Systems Engineering	6	6	307
5	Autonomous Systems	1	1	53

Paul Racunas

Publications

695

Citations

H-Index

Page 1

	Year	Citations
Computing Architectural Vulnerability Factors for Address-Based Structures Arijit Biswas, Paul Racunas, Razvan Cheveresan, ACM SIGARCH Computer Architecture News EngineeringComputer ArchitectureSoftware EngineeringArchitectural SupportProcessor Architecture	2005	184
Computing Architectural Vulnerability Factors for Address-Based Structures A. Biswas, Paul Racunas, Razvan Cheveresan, EngineeringComputer ArchitectureSoftware EngineeringArchitectural SupportProcessor Architecture	2005	154
Perturbation-based Fault Screening Paul Racunas, Kypros Constantinides, Srilatha Manne, EngineeringFault ScreenersVerificationComputer ArchitecturePerturbation-based Fault Screening	2007	120
Resiliency of automotive object detection networks on GPU architectures Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Object Detection OutcomesConvolutional Neural NetworkEngineeringMachine LearningComputer Architecture	2019	53
Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal A. Biswas, Paul Racunas, Joel Emer, IEEE Computer Architecture Letters Hardware ModelingEngineeringHardware Verification LanguageComputer ArchitectureSoftware Engineering	2008	41
Partitioned first-level cache design for clustered microarchitectures Paul Racunas, Yale N. Patt Cluster ComputingMemory ArchitectureClustered MicroarchitecturesEngineeringWire Delay	2003	40
Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order Jared Stark, Paul Racunas, Yale N. Patt International Symposium on Microarchitecture EngineeringMemory DesignComputer ArchitectureSoftware EngineeringProcessor Architecture	1997	40
Characterizing and Mitigating Soft Errors in GPU DRAM Michael B. Sullivan, N.R. Saxena, Mike O’Connor, Hardware SecurityHbm2 MemoryGpu ArchitectureEngineeringHardware Reliability	2021	32
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor Steven Raasch, Arijit Biswas, Jon Stephan, Port AvfsAccurate Analytical TechniqueEngineeringHardware AlgorithmComputer Architecture	2015	21
Characterizing and Mitigating Soft Errors in GPU DRAM Michael B. Sullivan, N.R. Saxena, Mike O’Connor, IEEE Micro	2022	10

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