Static Voltage Scaling

Static Voltage Scaling is a power management technique that reduces processor supply voltage and clock frequency to fixed, predetermined levels during system idle or low-activity periods, thereby minimizing dynamic and static power consumption without real-time adaptation.

19

Publications

852

Citations

95

Authors

43

Institutions

Publications per year

2017–2026

2

Variants

Svs

Authors

95

  1. MO
    Michael Orshansky

    The University of Texas at Austin, United States

    2 publications · 163 citations

    2

    h-index

  2. ZP
    Zebo Peng

    Linköping University, Sweden

    2 publications · 61 citations

    2

    h-index

  3. DC
    David Chinnery

    University of California, Berkeley, United States

    2 publications · 163 citations

    2

    h-index

  4. KK
    Kurt Keutzer

    University of California, Berkeley, United States

    2 publications · 163 citations

    2

    h-index

  5. AD
    Abhijit Davare

    University of California, Berkeley, United States

    2 publications · 163 citations

    2

    h-index

1–5 of 95

Venues

  1. IEEE Journal of Solid-State Circuits

    3 publications · 185 citations

    3

    h-index

  2. 2

    h-index

  3. 2

    h-index

  4. Microelectronics Reliability

    1 publications · 21 citations

    1

    h-index

  5. Integration

    1 publications · 12 citations

    1

    h-index

1–5