Sparse Computation Acceleration
Sparse Computation Acceleration is a coarse-grained reconfigurable architecture technique that exploits computational sparsity by selectively activating processing elements and bypassing zero-valued or pruned data operations to improve energy efficiency and throughput in sparse workloads.
227
Publications
17.1K
Citations
760
Authors
193
Institutions
Publications per year
2017–2026
129
227
Song Han, Xingyu Liu, Huizi Mao et al. · ACM SIGARCH Computer Architecture News · 2016 · 2K citations
EIE: Efficient Inference Engine on Compressed Deep Neural Network
Song Han, Xingyu Liu, Huizi Mao et al. · 2016 · 967 citations
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara et al. · 2017 · 927 citations
Cambricon-X: An accelerator for sparse neural networks
Shijin Zhang, Zidong Du, Lei Zhang et al. · 2016 · 597 citations
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Stanford University
Stanford, United States
12 h-index
34 publications
23.4K citations
Tsinghua University
Beijing, China
12 h-index
67 publications
2.7K citations
Georgia Institute of Technology
Atlanta, United States
11 h-index
34 publications
4.2K citations

Chinese Academy of Sciences
Beijing, China
10 h-index
61 publications
1.8K citations
Massachusetts Institute of Technology
Cambridge, United States
9 h-index
21 publications
4.5K citations
Institute of Computing Technology
Beijing, China
9 h-index
57 publications
3K citations
University of Tennessee at Knoxville
Knoxville, United States
9 h-index
29 publications
1.1K citations
Nvidia (United Kingdom)
Reading, United Kingdom
8 h-index
15 publications
4.6K citations
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Repository · 12 publications · 1.8K citations
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7 publications · 224 citations
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TOMS · 5 publications · 364 citations
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TPDS · 5 publications · 221 citations
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4 publications · 173 citations
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