Security Property Verification

Security Property Verification is a formal process within hardware security verification that establishes whether a hardware design conforms to specified security properties by systematically checking that the design's behavior adheres to predefined confidentiality, integrity, and availability requirements under adversarial conditions.

114

Publications

5.1K

Citations

322

Authors

120

Institutions

Publications per year

2017–2026

36

Authors

322

  1. YJ
    Yier Jin

    University of Central Florida, United States

    6 publications · 312 citations

    6

    h-index

  2. YM
    Yiorgos Makris

    The University of Texas at Dallas, United States

    6 publications · 295 citations

    6

    h-index

  3. RK
    Ryan Kastner

    University of California San Diego, United States

    5 publications · 245 citations

    5

    h-index

  4. PS
    Pramod Subramanyan

    Princeton University, United States

    5 publications · 179 citations

    5

    h-index

  5. WH
    Wei Hu

    Northwestern Polytechnical University, China

    5 publications · 236 citations

    5

    h-index

1–5 of 322

Venues

  1. 4

    h-index

  2. Journal of Computer Security

    4 publications · 175 citations

    4

    h-index

  3. ACM SIGOPS Operating Systems Review

    3 publications · 471 citations

    3

    h-index

  4. 2

    h-index

  5. IACR Cryptology ePrint Archive

    Repository · 2 publications · 25 citations

    2

    h-index

1–5