Reduced Instruction Set Computing
Reduced Instruction Set Computing is an instruction set architecture characterized by a small, highly optimized set of simple instructions that execute in a single clock cycle, emphasizing uniform instruction format and a load-store design to enhance processor efficiency and streamline hardware complexity.
155
Publications
8.9K
Citations
565
Authors
133
Institutions
Publications per year
2017–2026
19
Parents
155
Slither: A Static Analysis Framework for Smart Contracts
2019 · 758 citations · Full text
Reduced instruction set computers
David A. Patterson · Communications of the ACM · 1985 · 451 citations · Full text
A VLIW architecture for a trace scheduling compiler
Robert P. Colwell, Robert Nix, John J. O’Donnell et al. · ACM SIGOPS Operating Systems Review · 1987 · 400 citations
IBM's S/390 G5 microprocessor design
T. J. Slegel, R. M. Averill, M. A. Check et al. · IEEE Micro · 1999 · 349 citations
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133
University of California, Berkeley
Berkeley, United States
11 h-index
25 publications
2.2K citations
IBM (United States)
Armonk, United States
9 h-index
70 publications
9.2K citations
Stanford University
Stanford, United States
7 h-index
15 publications
536 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
5 h-index
9 publications
816 citations
Intel (United States)
Santa Clara, United States
4 h-index
6 publications
210 citations
IBM Research - Austin
Austin, United States
4 h-index
8 publications
340 citations
University of Michigan
Ann Arbor, United States
4 h-index
12 publications
772 citations
North Carolina State University
Raleigh, United States
3 h-index
5 publications
117 citations
1–8 of 133
10 publications · 637 citations
10
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8 publications · 343 citations
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7 publications · 447 citations
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7 publications · 492 citations
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6 publications · 127 citations
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