Reduced Instruction Set Computing

Reduced Instruction Set Computing is an instruction set architecture characterized by a small, highly optimized set of simple instructions that execute in a single clock cycle, emphasizing uniform instruction format and a load-store design to enhance processor efficiency and streamline hardware complexity.

155

Publications

8.9K

Citations

565

Authors

133

Institutions

Publications per year

2017–2026

19

Authors

565

  1. DA
    David A. Patterson

    University of California, Berkeley, United States

    7 publications · 617 citations

    7

    h-index

  2. DA
    David A. Patterson

    University of California, Berkeley, United States

    5 publications · 519 citations

    5

    h-index

  3. RN
    Robert Nix

    Yale University, United States

    4 publications · 747 citations

    4

    h-index

  4. DB
    David B. Papworth

    Intel (United States), United States

    4 publications · 747 citations

    4

    h-index

  5. CH
    Carlo H. Séquin

    University of California, Berkeley, United States

    4 publications · 237 citations

    4

    h-index

1–5 of 565

Venues

  1. Computer

    10 publications · 637 citations

    10

    h-index

  2. IEEE Journal of Solid-State Circuits

    8 publications · 343 citations

    8

    h-index

  3. ACM SIGARCH Computer Architecture News

    7 publications · 447 citations

    7

    h-index

  4. IEEE Micro

    7 publications · 492 citations

    7

    h-index

  5. IEEE Spectrum

    6 publications · 127 citations

    6

    h-index

1–5