Processor-in-the-loop Testing

Processor-In-The-Loop Testing is a validation methodology within embedded systems engineering that involves executing control algorithms on an actual physical processor while interfacing in real time with a simulated plant model, thereby enabling the assessment of processor-specific behaviors and timing characteristics under realistic operational conditions.

18

Publications

479

Citations

63

Authors

25

Institutions

Publications per year

2017–2026

10

Variants

Pil TestingProcessor-in-the-loop Simulation

Authors

63

  1. EC
    Eric C. Kerrigan

    Imperial College London, United Kingdom

    2 publications · 24 citations

    2

    h-index

  2. AS
    Andrea Suardi

    Imperial College London, United Kingdom

    2 publications · 24 citations

    2

    h-index

  3. BG
    B. G. Khusainov

    Imperial College London, United Kingdom

    2 publications · 24 citations

    2

    h-index

  4. GA
    George A. Constantinides

    Imperial College London, United Kingdom

    2 publications · 24 citations

    2

    h-index

  5. MH
    Min Hu

    China Academy Of Machinery Science & Technology (China), China

    1 publications · 16 citations

    1

    h-index

1–5 of 63

Venues

  1. IEEE Power Electronics Magazine

    1 publications · 41 citations

    1

    h-index

  2. IEEE/ASME Transactions on Mechatronics

    1 publications · 34 citations

    1

    h-index

  3. 1

    h-index

  4. IEEE Access

    1 publications · 45 citations

    1

    h-index

  5. Applied Sciences

    1 publications · 19 citations

    1

    h-index

1–5