Processor Security Verification

Processor Security Verification is a formal methodology within hardware security verification that specifically ensures processor designs enforce intended security properties by detecting and mitigating vulnerabilities in their microarchitectural and logical implementations.

33

Publications

1.5K

Citations

102

Authors

45

Institutions

Publications per year

2017–2026

13

Authors

102

  1. GE
    G. Edward Suh

    Cornell University, United States

    4 publications · 442 citations

    4

    h-index

  2. RZ
    Rui Zhang

    University of North Carolina at Chapel Hill, United States

    3 publications · 97 citations

    3

    h-index

  3. AR
    Alastair Reid

    ARM (United Kingdom), United Kingdom

    3 publications · 102 citations

    3

    h-index

  4. SD
    Srinivas Devadas

    Massachusetts Institute of Technology, United States

    3 publications · 394 citations

    3

    h-index

  5. CS
    Cynthia Sturton

    University of North Carolina at Chapel Hill, United States

    3 publications · 97 citations

    3

    h-index

1–5 of 102

Venues

  1. IEEE Transactions on Computers

    2 publications · 58 citations

    2

    h-index

  2. ACM SIGARCH Computer Architecture News

    2 publications · 45 citations

    2

    h-index

  3. Journal of Computer Security

    1 publications · 15 citations

    1

    h-index

  4. 1

    h-index

  5. Proceedings of the ACM on Programming Languages

    PACMPL · 1 publications · 17 citations

    1

    h-index

1–5