Primitive Instance
A Primitive Instance is a fundamental built-in logic element in Verilog syntax that directly represents a low-level digital circuit component, distinguished by its predefined behavioral or structural functionality at the gate or switch level.
7
Publications
1K
Citations
18
Authors
13
Institutions
Publications per year
2017–2026
4
Parents
7
1–5 of 7
18
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13

McGill University
Montreal, Canada
2 h-index
2 publications
199 citations
National Research Council Canada
Ottawa, Canada
2 h-index
2 publications
199 citations
Huawei Technologies (France)
Boulogne-Billancourt, France
1 h-index
3 publications
96 citations

South China University of Technology
Guangzhou, China
1 h-index
1 publications
13 citations
Rutgers Sexual and Reproductive Health and Rights
Utrecht, Netherlands
1 h-index
2 publications
1.4K citations
Wuhan University
Wuhan, China
1 h-index
1 publications
32 citations
Baidu (China)
Beijing, China
1 h-index
1 publications
706 citations
Microsoft Research Asia (China)
Beijing, China
1 h-index
4 publications
52 citations
1–8 of 13
1 publications · 32 citations
1
h-index
1 publications · 23 citations
1
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TPAMI · 1 publications · 182 citations
1
h-index
Conference · 1 publications · 32 citations
1
h-index
JAG · 1 publications · 10 citations
1–5