Primitive Instance

A Primitive Instance is a fundamental built-in logic element in Verilog syntax that directly represents a low-level digital circuit component, distinguished by its predefined behavioral or structural functionality at the gate or switch level.

7

Publications

1K

Citations

18

Authors

13

Institutions

Publications per year

2017–2026

4

Authors

18

  1. GR
    Gerhard Roth

    University of Bremen, Germany

    2 publications · 199 citations

    2

    h-index

  2. MD
    Martin D. Levine

    McGill University, Canada

    2 publications · 199 citations

    2

    h-index

  3. TX
    Tao Xu

    Lehigh University, United States

    1 publications · 706 citations

    1

    h-index

  4. TB
    Tom Brass

    University of Cambridge, United Kingdom

    1 publications · 32 citations

    1

    h-index

  5. XW
    Xiaogang Wang

    European Organization for Nuclear Research, Switzerland

    1 publications · 706 citations

    1

    h-index

1–5 of 18

Venues

  1. Capital & Class

    1 publications · 32 citations

    1

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  2. Science Technology & Human Values

    1 publications · 23 citations

    1

    h-index

  3. 1

    h-index

  4. 2021 IEEE/CVF International Conference on Computer Vision (ICCV)

    Conference · 1 publications · 32 citations

    1

    h-index

1–5