Power-aware Synthesis
Power-Aware Synthesis is a design methodology within the field of low-power FPGA design that integrates power consumption optimization during the logic synthesis phase by strategically manipulating resource allocation, technology mapping, and circuit structuring to minimize dynamic and static power, distinguishing it from conventional synthesis approaches that primarily target area and timing constraints.
185
Publications
5.8K
Citations
423
Authors
145
Institutions
Publications per year
2017–2026
15
Parents
185
Synthesis techniques for low-power hard real-time systems on variable voltage processors
Inki Hong, Gang Qu, Miodrag Potkonjak et al. · 2002 · 186 citations · Full text
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Princeton University
Princeton, United States
15 h-index
44 publications
1.4K citations
University of California, Los Angeles
Los Angeles, United States
12 h-index
25 publications
1.4K citations
University of California, Berkeley
Berkeley, United States
8 h-index
19 publications
1.1K citations
University of Southern California
Los Angeles, United States
8 h-index
15 publications
347 citations
Politecnico di Torino
Turin, Italy
7 h-index
25 publications
634 citations
University of Illinois Urbana-Champaign
Urbana, United States
7 h-index
13 publications
348 citations
Carl von Ossietzky Universität Oldenburg
Oldenburg, Germany
6 h-index
8 publications
195 citations
Northwestern University
Evanston, United States
6 h-index
15 publications
398 citations
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10 publications · 516 citations
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9 publications · 550 citations
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TODAES · 4 publications · 181 citations
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3 publications · 68 citations
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2 publications · 40 citations
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