Power-aware Synthesis

Power-Aware Synthesis is a design methodology within the field of low-power FPGA design that integrates power consumption optimization during the logic synthesis phase by strategically manipulating resource allocation, technology mapping, and circuit structuring to minimize dynamic and static power, distinguishing it from conventional synthesis approaches that primarily target area and timing constraints.

185

Publications

5.8K

Citations

423

Authors

145

Institutions

Publications per year

2017–2026

15

Authors

423

  1. NK
    Niraj K. Jha

    Princeton University, United States

    14 publications · 435 citations

    13

    h-index

  2. AR
    Anand Raghunathan

    Princeton University, United States

    9 publications · 397 citations

    9

    h-index

  3. DC
    Deming Chen

    University of Illinois Urbana-Champaign, United States

    6 publications · 184 citations

    6

    h-index

  4. GL
    G. Lakshminarayana

    Princeton University, United States

    5 publications · 132 citations

    5

    h-index

  5. EM
    Enrico Macii

    Politecnico di Torino, Italy

    5 publications · 108 citations

    5

    h-index

1–5 of 423

Venues

  1. 10

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  2. 9

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  3. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 4 publications · 181 citations

    4

    h-index

  4. Integration

    3 publications · 68 citations

    3

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  5. 2

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1–5