Parity Generation

Parity Generation is a combinational logic function that belongs to the class of error-detection mechanisms, specifically defined as the process of computing a binary output bit such that the total number of 1s in a given data word and the parity bit together satisfies a predetermined even or odd condition.

52

Publications

1.6K

Citations

138

Authors

71

Institutions

Publications per year

2017–2026

13

Authors

138

  1. SM
    Sourangshu Mukhopadhyay

    University of Burdwan, India

    2 publications · 64 citations

    2

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  2. UR
    Utpal Roy

    2 publications · 30 citations

    2

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  3. KQ
    Kai Qian

    Institute of Physics, China

    1 publications · 15 citations

    1

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  4. CC
    Ching-Che Chung

    National Chung Cheng University, Taiwan

    1 publications · 37 citations

    1

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  5. SR
    Sumathi Rao

    Harish-Chandra Research Institute, India

    1 publications · 24 citations

    1

    h-index

1–5 of 138

Venues

  1. Zenodo (CERN European Organization for Nuclear Research)

    Repository · 2 publications · 30 citations

    2

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  2. Optics Communications

    2 publications · 106 citations

    2

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  3. Physical Review Letters

    PRL · 2 publications · 63 citations

    2

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  4. 2

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  5. Electronics Letters

    2 publications · 60 citations

    2

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1–5