Network Packet Processing Accelerators

Network Packet Processing Accelerators is a class of reconfigurable accelerators that specializes in high-throughput, low-latency manipulation and analysis of network packets by leveraging customizable hardware architectures to dynamically adapt to varying packet processing tasks such as filtering, classification, forwarding, and encryption.

36

Publications

941

Citations

172

Authors

61

Institutions

Publications per year

2017–2026

15

Authors

172

  1. LK
    Lazaros Koromilas

    University of Crete, Greece

    3 publications · 90 citations

    3

    h-index

  2. GV
    Giorgos Vasiliadis

    Columbia University, United States

    3 publications · 90 citations

    3

    h-index

  3. GK
    G. Konstantoulakis

    Ellemedia Technologies (Greece), Greece

    2 publications · 26 citations

    2

    h-index

  4. HW
    H. Wilson

    Intel (United States), United States

    2 publications · 59 citations

    2

    h-index

  5. JH
    Jason Howard

    Intel (United States), United States

    2 publications · 59 citations

    2

    h-index

1–5 of 172

Venues

  1. Computer Communications

    3 publications · 46 citations

    3

    h-index

  2. Microprocessors and Microsystems

    MICPRO · 3 publications · 43 citations

    3

    h-index

  3. USENIX Annual Technical Conference

    Conference · 2 publications · 95 citations

    2

    h-index

  4. Networked Systems Design and Implementation

    Conference · 1 publications · 37 citations

    1

    h-index

  5. IEEE Communications Surveys & Tutorials

    ComST · 1 publications · 47 citations

    1

    h-index

1–5