Netlist Hierarchy

Netlist Hierarchy is a hierarchical representation of an electronic circuit's connectivity, structured as a directed acyclic graph in which nodes denote circuit components or subcircuits and edges represent electrical nets, thereby organizing the netlist into nested levels of functional abstraction to facilitate modular design and analysis.

25

Publications

586

Citations

72

Authors

30

Institutions

Publications per year

2017–2026

4

Authors

72

  1. SS
    Sachin S. Sapatnekar

    University of Minnesota, United States

    2 publications · 86 citations

    2

    h-index

  2. AS
    Arvind Sharma

    University of Minnesota, United States

    2 publications · 86 citations

    2

    h-index

  3. DA
    Dan Alexandrescu

    Amplitude Technologies (France), France

    2 publications · 30 citations

    2

    h-index

  4. JH
    Jiang Hu

    Texas A&M University, United States

    2 publications · 86 citations

    2

    h-index

  5. RH
    Ramesh Harjani

    University of Minnesota, United States

    2 publications · 86 citations

    2

    h-index

1–5 of 72

Venues

  1. 6

    h-index

  2. Design Automation Conference

    Conference · 2 publications · 34 citations

    2

    h-index

  3. Network Computation in Neural Systems

    2 publications · 67 citations

    2

    h-index

  4. IEEE Design & Test of Computers

    2 publications · 29 citations

    2

    h-index

  5. 1

    h-index

1–5