Netlist Hierarchy
Netlist Hierarchy is a hierarchical representation of an electronic circuit's connectivity, structured as a directed acyclic graph in which nodes denote circuit components or subcircuits and edges represent electrical nets, thereby organizing the netlist into nested levels of functional abstraction to facilitate modular design and analysis.
25
Publications
586
Citations
72
Authors
30
Institutions
Publications per year
2017–2026
4
Parents
25
1–5 of 25
72
2
h-index
2
h-index
2
h-index
2
h-index
2
h-index
1–5 of 72
30
Intel (United States)
Santa Clara, United States
5 h-index
6 publications
200 citations
University of Washington
Seattle, United States
3 h-index
7 publications
153 citations
Texas A&M University
College Station, United States
2 h-index
4 publications
172 citations

University of Minnesota
Minneapolis, United States
2 h-index
12 publications
484 citations
Instituto Superior Técnico
Lisbon, Portugal
1 h-index
1 publications
61 citations
Carnegie Mellon University
Pittsburgh, United States
1 h-index
2 publications
52 citations
Instituto Politécnico de Lisboa
Lisbon, Portugal
1 h-index
1 publications
61 citations

University of Duisburg-Essen
Essen, Germany
1 h-index
1 publications
24 citations
1–8 of 30
6 publications · 194 citations
6
h-index
Conference · 2 publications · 34 citations
2
h-index
2 publications · 67 citations
2
h-index
2 publications · 29 citations
2
h-index
Conference · 1 publications · 11 citations
1
h-index
1–5