Multiple-issue Architectures
Multiple-Issue Architectures is a processor design paradigm in computer architecture that enables the simultaneous dispatch and execution of multiple instructions per clock cycle, distinguishing it from single-issue architectures by exploiting instruction-level parallelism through hardware-based dynamic scheduling and resource duplication.
57
Publications
5.9K
Citations
215
Authors
55
Institutions
Publications per year
2017–2026
1
Variants
Multiple-issue Processor Architectures
Parents
57
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy · 1995 · 1.4K citations · Full text
Dean M. Tullsen, Susan J. Eggers, Joel Emer et al. · 1996 · 782 citations
Pohua P. Chang, Scott Mahlke, William Y. Chen et al. · 1991 · 309 citations
1–5 of 57
215
7
h-index
7
h-index
7
h-index
3
h-index
3
h-index
1–5 of 215
55
University of Washington
Seattle, United States
7 h-index
22 publications
10.2K citations
Digital Wave (United States)
Centennial, United States
7 h-index
21 publications
2.8K citations
University of Illinois Urbana-Champaign
Urbana, United States
5 h-index
19 publications
2.3K citations
Hewlett-Packard (United States)
Palo Alto, United States
4 h-index
10 publications
928 citations
University of Wisconsin–Madison
Madison, United States
3 h-index
5 publications
398 citations
Intel (United States)
Santa Clara, United States
3 h-index
3 publications
53 citations

Delft University of Technology
Delft, The Netherlands
2 h-index
5 publications
84 citations
University of Hertfordshire
Hatfield, United Kingdom
2 h-index
8 publications
116 citations
1–8 of 55
6 publications · 446 citations
6
h-index
Repository · 1 publications · 148 citations
1
h-index
1 publications · 69 citations
1
h-index
MICPRO · 1 publications · 36 citations
1
h-index
1 publications · 12 citations
1
h-index
1–5