Module Declaration is a syntactic construct in Verilog that specifies the interface and identity of a hardware building block by defining its name, ports, and port directions, distinguishing it as the foundational unit for hierarchical design instantiation and structural composition.
12
Publications
594
Citations
17
Authors
7
Institutions
Publications per year
2017–2026
0
Parents
Publications
12
David MacQueen · 1984 · 270 citations · Full text
Module reuse by interface adaptation
James Purtilo, Joanne M. Atlee · Software Practice and Experience · 1991 · 81 citations
David Gries, Jan F. Prins · 1985 · 43 citations · Full text
1–5 of 12
Authors
17
- JF
2
h-index
- DG
2
h-index
- DM
1
h-index
- ME
1
h-index
- JM
1
h-index
1–5 of 17
Institutions
7
Laboratoire d'Informatique de Paris-Nord
Villetaneuse, France
2 h-index
4 publications
108 citations
AT&T (United States)
Bedminster, United States
1 h-index
1 publications
270 citations
Arizona State University
Tempe, United States
1 h-index
1 publications
15 citations
Wesleyan University
Middletown, United States
1 h-index
1 publications
40 citations
University of Maryland, College Park
College Park, United States
1 h-index
2 publications
162 citations
Auburn University
Auburn, United States
1 h-index
1 publications
40 citations
Stanford University
Stanford, United States
1 h-index
2 publications
24 citations
1–7 of 7
Venues
- ACM SIGPLAN Notices
2 publications · 26 citations
2
h-index
- Centrum Wiskunde & Informatica (CWI), the national research institute for mathematics and computer science in the Netherlands
Repository · 1 publications · 66 citations
1
h-index
- eScholarship (California Digital Library)
Repository · 1 publications · 15 citations
1
h-index
- IEEE Transactions on Software Engineering
TSE · 1 publications · 40 citations
1
h-index
- Software Practice and Experience
1 publications · 81 citations
1
h-index
1–5