Microarchitectural Security Verification

Microarchitectural Security Verification is a formal methodology within hardware security verification that specifically ensures the absence of security vulnerabilities in the microarchitectural design of a processor by rigorously analyzing its transient execution behaviors, data forwarding mechanisms, and resource sharing policies against defined security properties.

65

Publications

2.4K

Citations

214

Authors

91

Institutions

Publications per year

2017–2026

27

Authors

214

  1. GE
    G. Edward Suh

    Cornell University, United States

    6 publications · 338 citations

    6

    h-index

  2. AC
    Andrew C. Myers

    Cornell University, United States

    5 publications · 321 citations

    5

    h-index

  3. DZ
    Danfeng Zhang

    Pennsylvania State University, United States

    4 publications · 309 citations

    4

    h-index

  4. CB
    Christoph Baumann

    KTH Royal Institute of Technology, Sweden

    3 publications · 116 citations

    3

    h-index

  5. YJ
    Yier Jin

    University of Central Florida, United States

    2 publications · 67 citations

    2

    h-index

1–5 of 214

Venues

  1. arXiv (Cornell University)

    Repository · 3 publications · 90 citations

    3

    h-index

  2. ACM SIGPLAN Notices

    2 publications · 104 citations

    2

    h-index

  3. IEEE Micro

    2 publications · 56 citations

    2

    h-index

  4. Microprocessors and Microsystems

    MICPRO · 1 publications · 19 citations

    1

    h-index

  5. IEEE Access

    1 publications · 41 citations

    1

    h-index

1–5