Memory Level Parallelism

Memory Level Parallelism is a computer architecture concept that denotes the degree to which a processor can simultaneously initiate and sustain multiple memory accesses to different memory locations, thereby exploiting parallelism inherent in memory operations to improve performance.

116

Publications

7.7K

Citations

308

Authors

101

Institutions

Publications per year

2017–2026

22

Authors

308

  1. OM
    Onur Mutlu

    Carnegie Mellon University, United States

    8 publications · 865 citations

    8

    h-index

  2. LE
    Lieven Eeckhout

    Ghent University, Belgium

    7 publications · 181 citations

    7

    h-index

  3. MK
    Mahmut Kandemir

    Pennsylvania State University, United States

    6 publications · 251 citations

    6

    h-index

  4. MV
    Mateo Valero

    Universitat Politècnica de Catalunya, Spain

    4 publications · 101 citations

    4

    h-index

  5. YN
    Yale N. Patt

    The University of Texas at Austin, United States

    4 publications · 633 citations

    4

    h-index

1–5 of 308

Venues

  1. ACM SIGARCH Computer Architecture News

    6 publications · 861 citations

    6

    h-index

  2. IEEE Transactions on Computers

    4 publications · 79 citations

    4

    h-index

  3. IEEE Computer Architecture Letters

    3 publications · 55 citations

    3

    h-index

  4. ACM Transactions on Architecture and Code Optimization

    TACO · 3 publications · 55 citations

    3

    h-index

  5. International Journal of Parallel Programming

    2 publications · 26 citations

    2

    h-index

1–5