Memory Level Parallelism
Memory Level Parallelism is a computer architecture concept that denotes the degree to which a processor can simultaneously initiate and sustain multiple memory accesses to different memory locations, thereby exploiting parallelism inherent in memory operations to improve performance.
116
Publications
7.7K
Citations
308
Authors
101
Institutions
Publications per year
2017–2026
22
Parents
116
Computer architecture and parallel processing
Yigal Hoffner · Microprocessors and Microsystems · 1985 · 1.2K citations
A preliminary architecture for a basic data-flow processor
Jack B. Dennis, David P. Misunas · 1998 · 372 citations · Full text
A Case for MLP-Aware Cache Replacement
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu et al. · ACM SIGARCH Computer Architecture News · 2006 · 272 citations
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Pennsylvania State University
State College, United States
10 h-index
24 publications
1.3K citations
Carnegie Mellon University
Pittsburgh, United States
10 h-index
18 publications
780 citations
University of Illinois Urbana-Champaign
Urbana, United States
7 h-index
22 publications
1.5K citations
The University of Texas at Austin
Austin, United States
7 h-index
18 publications
2.5K citations
University of Wisconsin–Madison
Madison, United States
5 h-index
9 publications
219 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
5 h-index
18 publications
569 citations
Georgia Institute of Technology
Atlanta, United States
4 h-index
13 publications
287 citations

Barcelona Supercomputing Center
Barcelona, Spain
4 h-index
9 publications
298 citations
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6 publications · 861 citations
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4 publications · 79 citations
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3 publications · 55 citations
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TACO · 3 publications · 55 citations
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2 publications · 26 citations
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